Interrupt latency includes a number of clock cycles between an assertion of an interrupt by an interrupt source and execution of an initial non-prologue instruction in an interrupt service routine (ISR). The interrupt latency includes a cause latency, a selection latency, and a funnel latency. The cause latency is a number of cycles for a processor to determine that an interrupt is a reason to arrive at an address of an initial instruction of the ISR. The selection latency is a number of clock cycles for the processor to choose among multiple interrupts. The funnel latency includes a number of clock cycles in an interrupt funnel. The funnel latency includes a context overhead, a real-time operating system (RTOS) overhead, and a call overhead. The context overhead includes a number of clock cycles to save a state, such as data within a register file, before calling the ISR. The RTOS overhead includes a number of clock cycles for the processor to inform the RTOS that the ISR is entered into and exited from. The call overhead includes a number of clock cycles executed to obtain an address of the ISR and to prepare function arguments for calling the ISR.
An interrupt handler saves a portion of the register file of the processor to a bulk memory before executing the ISR. The time used to save the portion of the register file to the bulk memory is counted against the processor's interrupt latency. The time used to save the portion of the register file can be significant. For many real-time systems, such as, Bosch® Automotive Antilock Braking System (ABS) brake-system controller, the worst-case interrupt-latency matters. When saving the portion of the register file to the bulk memory, the worst-case interrupt latency can be high. For example, for the Nios II processor architecture, the worst-case interrupt latency for many real systems can be hundreds of processor clock cycles.